Among semiconductor devices, a DRAM includes a cell region, a peripheral circuit region, and a core region. The cell region is used to store data. The peripheral circuit region is used to convert an external voltage into an internal voltage or mediate signal transmission inside and outside a semiconductor chip, including a cell. The core region is used, when data is to be written in a cell or data stored in a cell is to be read, to selectively control word and bit lines connected to the corresponding cell.
In general, a pattern having the smallest width is formed in the cell region of a DRAM, and the peripheral circuit region is provided with a pattern having a larger width and free area than those of the cell region. The core region is provided with an amplification device referred to as a sense amplifier, which includes very complicated circuits. This means that the core region requires a fine design rule comparable to that of the cell region. In some cases, the pattern in the core region is smaller than that in the cell region, due to the current trend towards high integration of devices.
A conventional method for forming a sense amplifier will now be described with reference to FIGS. 1A to 1E.
FIGS. 1A and 1E are top views showing a series of process steps used in a conventional method for forming a sense amplifier.
Referring to FIG. 1A, a device isolation layer 110 is formed in a sense amplifier formation region of a semiconductor substrate 100 so that an active region for forming a sense amplifier is delimited. The active region includes an NMOS formation region 120a, a PMOS formation region 130a, an N+ pickup formation region 120b, and a P+ pickup formation region 130b. 
A gate insulation layer, a gate conduction layer, and a hard mask layer are laminated on the substrate so as to form gates 140 in a ring shape. Particularly, N-type gates are formed in the NMOS and PMOS formation regions, and those of the gates 140 formed on the device isolation layer 110 outside the active region are supposed to have contacts between the gates 140 and a wiring.
Referring to FIG. 1B, a buffer oxide layer (not shown) and a spacer nitride layer (not shown) are successively formed on the front surface of the resulting substrate, which have the gates 140 formed thereon. Then, an insulation layer (not shown) is formed on the spacer nitride layer so as to cover the gates.
A first mask pattern M1, which has line-type openings for exposing the NMOS formation region 120a and the N+ pickup formation region 120b, is formed on the insulation layer. The insulation layer in the exposed NMOS formation region 120a and N+ pickup formation region 120b is etched by using the first mask pattern M1 as an etching mask. The underlying spacer nitride layer and buffer oxide layer are subjected to anisotropic etching so that spacers (not shown) are formed on lateral walls of the gates 140 while exposing the active region of the substrate among the gates 140, as well as the N+ pickup formation region 120b. 
An N-type impurity is ion-implanted into the active region of the substrate, which has been exposed among the gates 140 in the NMOS formation region 120a, and into the exposed N+ pickup formation region 120b so as to form an N+ junction region 150a and an N+ pickup region 150b. 
Referring to FIG. 1C, the first mask pattern M1 is removed, and a second mask pattern M2, which has line-type openings for selectively exposing the PMOS formation region 130a and a part of the P+ pickup formation region 130b, is formed on the front surface of the resulting substrate. The insulation layer in the exposed PMOS formation region 130a and P+ pickup formation region 130b is etched by using the second mask pattern M2 as an etching mask. The underlying spacer nitride layer and buffer oxide layer are subjected to anisotropic etching so that spacers (not shown) are formed on the lateral walls of the gates 140 while exposing the active region of the substrate among the gates 140, as well as the P+ pickup formation region 130b. 
A P-type impurity is ion-implanted into the active region, which has been exposed among the gates 140 in the PMOS formation region 130a, and into the exposed P+ pickup formation region 130b so as to form a P+ junction region 160a and an P+ pickup region 160b. 
The second mask pattern M2 is designed so as to cover intermediate parts of the P+ pickup formation region 130b so that a pattern of laminated buffer oxide layer, spacer nitride layer, and insulation layer remains on the covered parts. This is for the purpose of connecting a pattern of laminated buffer oxide layer, spacer nitride layer, and insulation layer, which remains to the left of the P+ pickup formation region 130b, to that remaining to the right thereof. The resulting pattern of laminated buffer oxide layer, spacer nitride layer, and insulation layer has a locally H-shaped configuration.
If the second mask pattern M2 leaves the P+ pickup formation region 130b completely exposed, i.e. if no pattern of laminated buffer oxide layer, spacer nitride layer, and insulation layer remains in the P+ pickup formation region 130b, the patterns of laminated buffer oxide layer, spacer nitride layer, and insulation layer, which remain to the left and right of the P+ pickup formation region 130b, respectively, are elongated in y-axis direction without a supporter extending in x-axis direction and connecting them to each other. This means that the left and right patterns are structurally unstable, i.e. likely to deform. Therefore, the second mask pattern M2 must cover parts of the P+ pickup formation region 130b. It is to be noted that no bit line contact hole is formed on the covered parts at a later time.
Although the pattern of laminated buffer oxide layer, spacer nitride layer, and insulation layer, which remains between the N+ pickup region 150b and the PMOS region, is elongated in the y-axis direction, there is no possibility that the pattern may deform, because it makes contact with the gates 140 in the PMOS region.
Referring to FIG. 1D, the second mask pattern M2 is removed, and a first insulation interlayer is formed so as to cover the resulting substrate. The first insulation interlayer is subjected to etch-back or CMP (chemical mechanical polishing) until the gates 140 are exposed. A second insulation interlayer is formed on the first insulation interlayer. Predetermined portions of the first and second insulation interlayers are etched so as to form bit line contact holes 170 for exposing the N+ junction region 150a, the P+ junction region 160a, the N+ pickup region 150b, and the P+ pickup region 160b, respectively. In addition, bit line contact holes 170 are also formed so as to expose the gates 140 formed on the device isolation layer 110 outside the active region.
A third mask pattern M3 is formed on the resulting substrate, which has the bit line contact holes 170 formed thereon, in the same manner as the second mask pattern M2. Particularly, the third mask pattern M3 has line-type openings for exposing the P+ junction region 160a and a part of the P+ pickup region 160b, but does not expose intermediate parts of the P+ pickup region 160b. 
Additional ion implantation is performed inside the bit line contact holes 170 in the P+ junction region 160a and the P+ pickup region 160b, which have been exposed by the third mask pattern M3. In general, the additional ion implantation is performed only in the P+ junction region 160a and the P+ pickup region 160b, but not in the NMOS region and the N+ pickup region 150b. This is because the P-type impurity resolves more easily than the N-type impurity, and the resulting increase in contact resistance in the P+ junction region 160a and the P+ pickup region 160b must be compensated for. In other words, additional ion implantation in the region, which is supposed to have contacts formed therein, increases the doping density of the contact interface and decreases the contact resistance.
The additional ion implantation is not performed inside the bit line contact holes 170, which are formed on the gates 140 outside the active region, because ion implantation of a P-type impurity into the gates 140, which are N-type gates, increases the resistance.
Referring to FIG. 1E, the third mask pattern M3 is removed, and a cleaning process is performed so as to remove impurities from inside the bit line contact holes 170. During the cleaning process, the second insulation interlayer outside the bit line contact holes 170 partially loses its thickness.
Although not shown in the drawings, a bit line conduction layer is deposited on the second insulation interlayer by using tungsten, for example, so as to fill the bit line contact holes 170, which have been cleaned. The bit line conduction layer is patterned so as to form bit lines, which make contact with the N+ junction region 150a, the P+ junction region 160a, the N+ pickup region 150b, the P+ pickup region 160b, and the gates 140, respectively.
Thereafter, a series of conventional processes are further performed so as to complete a sense amplifier of the semiconductor device.
However, the conventional processes have a problem in that the P+ pickup region 160b is partially covered during additional ion implantation, because the mask pattern used for the additional ion implantation (i.e. the third mask pattern M3) has the same shape as that of the second mask pattern M2. This means that additional ion implantation is not performed to a portion of the second insulation interlayer, which corresponds to the covered part of the P+ pickup region 160b. 
When the P+ pickup region 160b has a part which has not been subjected to additional ion implantation, the amount of loss of thickness of the second insulation interlayer occurring on the part which has been subjected to additional ion implantation differs from that occurring on the part which has not, when the bit line contact holes 170 are cleaned in a subsequent process. This is because the part that has been subjected to additional ion implantation has a faster loss rate during cleaning due to damage resulting from ions.
As a result, a stepped portion is created on the second insulation interlayer before a bit line conduction layer is deposited. Although such a stepped portion causes little problem in the case of a device having a line width of at least 100 nm, it is problematic in the case of a highly-integrated device having a line width of less than 100 nm. Particularly, high integration of devices decreases the line width of bit lines, as well as the spacing between them. Consequently, the process for patterning the bit line conduction layer becomes more difficult. The stepped portion on the second insulation interlayer degrades the degree of surface flatness of the bit line conduction layer. This decreases the DOF (depth of focus) margin during an exposure process for forming bit lines and, as a result, causes defective patterning, such as bridging between bit lines.
FIG. 2 is a sectional view taken along line a-a′ of FIG. 1E and shows a stepped portion, which has been created on the second insulation interlayer ILD2 when the bit line contact holes 170 are cleaned, after the bit line conduction layer 180 is deposited, but before the bit line conduction layer 180 is patterned. Reference numeral ILD1 refers to the first insulation interlayer.